1. Field of the Invention
The present invention relates to a semiconductor device and a process for the production thereof and more particularly to a semiconductor device having multilevel interconnections and a process for the production thereof.
2. Description of the Prior Art
In recent years, the integration density of semiconductor devices has been raised and the mutilevel interconnections have been used more frequently, as the scale of the system realized by the use of semiconductor devices is increased and the fabrication technology for semiconductor devices with fine geometry is advanced.
With the increase in the integration density of semiconductor devices, the space between the interconnections also decreases. Because of this, the parasitic capacitance incidental to the interconnections increases.
In order to reduce such parasitic capacitance, it has been proposed to remove an inter-layer insulation film to make the space between the interconnection layers vacant, by supporting the upper layer interconnections only by contact pillars at via hole positions, in a report by Eiichi YAMAMOTO, et al. entitled "Multilevel Metal Interconnect for Ultra Speed LSI using Al/Polymide Contact Method" numbered 456 in a preprint article of "Electronic Information Communication Society 70th Anniversary General National Grand Meeting" (1987) at pages 2-260. In such multilevel interconnections of aerial interconnection construction as above, the coupling capacitance between interconnection levels is reduced to 1/4 to1/3 of that of ordinary multilevel interconnections completely filled with inter-layer insulating films.
The above-mentioned prior art multi-level interconnections having aerial interconnection construction is considered to have ideal construction with respect to reduction of coupling capacitance between interconnection levels, but to have a defect that is to weak against mechanical impact since the phsical support between imterconnection levels is achieved only bt conductive contact pillars for electrically connecting interconnection levels. Further, thermal stress of interconnections caused by thermal expansion owing to Joule's heat is not dispersed but concentrated to the contact pillars. For such thermal and mechanical impacts, it is liable to occur that interconnections are cut open or short-circuited and so it is impracticable to really apply the multilevel interconnections having aerial interconnection construction to a large scale intergrated circuit.
The present inventor formerly presented together with other co-inventors, in U. S. Ser. No. 07/511885 filed on Apr. 20, 1990 a semiconductor device that has a feature in the spatial relationship between interconnection levels and the intermediate insulating films. In the lower part of the second and/or subsequent levels of interconnection there exist intermediate insulating films that have a pattern which is the same as the pattern of the interconnection. Becuase of this arrangement, the intermediate insulating film does not exist between the interconnections on the same level. The first structure of the multilevel interconnection has the intermediate insulating films formed in wall-like shape, with the lower end of the intermediate insulating films reaching an underlying insulating layer formed on the surface of the semiconducture substrate. The second structure of the multilevel interconnection is a quasi air gap metallization structure. This construction has markedly improved thermal and mechanical strength compared with the above-mentioned aerial interconnection construction, but the reduction of coupling capacitance between interconnection levels is not so large as the aerial interconnection construction.